1. Field of the Invention
The present invention relates to a device structure of an integrated circuit. More particularly, the present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of Related Art
In semiconductor devices fabricated using silicon metal oxide, when the gate length is scaled down to deep sub-micron level, the time required for charge carriers to travel is shortened, improving the overall efficiency of the device. Nonetheless, the techniques required to shrink the gate length are still under development since there are numerous problems to be overcome.
Currently, to obtain more excellent device efficiency efficient, techniques for fabricating source/drain of metal-oxide-semiconductor transistors using a SiGe process has been actively developing. SiGe materials can be selectively grown on the source/drain regions. In contrast to silicon and silicon oxide, SiGe materials can also be selectively etched.
Usually, the source/drain region fabricated by SiGe process is doped with highly concentrated boron to decrease the resistance. Moreover, in transistor devices using a SiGe layer heavily doped with boron as the source/drain regions, the higher the dopant concentration, the better the current gain for the device. Nevertheless, the boron dopants in the SiGe inevitably diffuse out of the source/drain regions. If the boron dopant diffuses out vertically, the junction depth will be too deep and problems like punch through effect arise. If the boron dopant diffuses out horizontally, short channel effect will occur, affecting the overall efficiency of the device.
Therefore, to fabricate source/drain regions of the transistor devices using SiGe without the above-mentioned problems has become the main focus of development in the industry.